Complete step463 assembly generators and x86-to-arm mapping tests
This commit is contained in:
Bill
@@ -3046,4 +3046,13 @@ target_link_libraries(step462_test PRIVATE
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tree_sitter_javascript tree_sitter_typescript
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tree_sitter_java tree_sitter_rust tree_sitter_go)
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add_executable(step463_test tests/step463_test.cpp)
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target_include_directories(step463_test PRIVATE src)
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target_link_libraries(step463_test PRIVATE
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nlohmann_json::nlohmann_json
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unofficial::tree-sitter::tree-sitter
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tree_sitter_python tree_sitter_cpp tree_sitter_elisp
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tree_sitter_javascript tree_sitter_typescript
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tree_sitter_java tree_sitter_rust tree_sitter_go)
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# Step 12: Dear ImGui shell scaffolding created (main.cpp exists but not built due to dependencies)
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167
editor/src/ast/AssemblyGenerator.h
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167
editor/src/ast/AssemblyGenerator.h
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@@ -0,0 +1,167 @@
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#pragma once
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// Step 463: Assembly Generator (x86 + ARM)
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// Generates assembly text from Assembly AST nodes and provides a simple
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// cross-architecture mapper for basic instruction sequences.
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#include "AssemblyNodes.h"
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#include "EnumNamespaceNodes.h"
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#include "Function.h"
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#include "Module.h"
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#include <algorithm>
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#include <sstream>
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#include <string>
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#include <vector>
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enum class X86OutputSyntax {
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Intel,
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ATT
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};
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class AssemblyGenerator {
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public:
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static std::string commentPrefix(const std::string& arch) {
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if (arch == "x86") return "; ";
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if (arch == "arm") return "@ ";
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return "; ";
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}
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static std::string generateX86(const Module& module,
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X86OutputSyntax syntax = X86OutputSyntax::Intel) {
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std::ostringstream out;
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emitModuleDirectives(module, out);
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for (auto* fnNode : module.getChildren("functions")) {
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if (fnNode->conceptType != "Function") continue;
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auto* fn = static_cast<Function*>(fnNode);
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emitFunctionX86(*fn, out, syntax);
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}
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return out.str();
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}
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static std::string generateArm(const Module& module) {
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std::ostringstream out;
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emitModuleDirectives(module, out);
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for (auto* fnNode : module.getChildren("functions")) {
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if (fnNode->conceptType != "Function") continue;
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auto* fn = static_cast<Function*>(fnNode);
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emitFunctionArm(*fn, out);
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}
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return out.str();
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}
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static std::vector<AssemblyInstruction> translateX86ToArmSimple(
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const std::vector<AssemblyInstruction>& x86Instructions) {
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std::vector<AssemblyInstruction> out;
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for (const auto& i : x86Instructions) {
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std::string op = toLower(i.opcode);
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AssemblyInstruction mapped;
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mapped.operands = i.operands;
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if (op == "mov" || op == "movq" || op == "movl") mapped.opcode = "mov";
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else if (op == "add" || op == "addq" || op == "addl") mapped.opcode = "add";
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else if (op == "sub" || op == "subq" || op == "subl") mapped.opcode = "sub";
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else if (op == "cmp" || op == "cmpq" || op == "cmpl") mapped.opcode = "cmp";
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else if (op == "jmp") mapped.opcode = "b";
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else if (op == "call") mapped.opcode = "bl";
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else if (op == "ret") mapped.opcode = "ret";
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else mapped.opcode = op;
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out.push_back(std::move(mapped));
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}
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return out;
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}
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private:
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static std::string toLower(std::string s) {
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std::transform(s.begin(), s.end(), s.begin(),
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[](unsigned char c){ return static_cast<char>(std::tolower(c)); });
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return s;
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}
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static std::string emitDirective(const AssemblyDirective& d) {
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if (d.value.empty()) return directiveTypeToString(d.type);
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return directiveTypeToString(d.type) + " " + d.value;
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}
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static std::string formatOperandX86(const std::string& operand, X86OutputSyntax syntax) {
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if (syntax == X86OutputSyntax::Intel) return operand;
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std::string o = operand;
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// naive register sigil conversion for AT&T
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if (!o.empty() && o[0] != '[' && o[0] != '%' && std::isalpha(static_cast<unsigned char>(o[0]))) {
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bool maybeReg = true;
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for (char c : o) {
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if (!(std::isalnum(static_cast<unsigned char>(c)) || c == '_')) {
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maybeReg = false;
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break;
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}
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}
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if (maybeReg) o = "%" + o;
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}
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if (!o.empty() && std::isdigit(static_cast<unsigned char>(o[0]))) {
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o = "$" + o;
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}
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return o;
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}
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static void emitFunctionX86(const Function& fn, std::ostringstream& out, X86OutputSyntax syntax) {
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out << fn.name << ":\n";
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for (auto* n : fn.getChildren("body")) {
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if (n->conceptType == "AssemblyLabel") continue; // function name already emitted
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if (n->conceptType == "AssemblyInstruction") {
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auto* i = static_cast<AssemblyInstruction*>(n);
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out << " " << i->opcode;
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if (!i->operands.empty()) {
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out << " ";
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for (size_t k = 0; k < i->operands.size(); ++k) {
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out << formatOperandX86(i->operands[k], syntax);
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if (k + 1 < i->operands.size()) out << ", ";
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}
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}
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out << "\n";
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} else if (n->conceptType == "AssemblyDirective") {
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auto* d = static_cast<AssemblyDirective*>(n);
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out << " " << emitDirective(*d) << "\n";
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}
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}
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}
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static void emitFunctionArm(const Function& fn, std::ostringstream& out) {
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out << fn.name << ":\n";
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for (auto* n : fn.getChildren("body")) {
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if (n->conceptType == "AssemblyLabel") continue;
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if (n->conceptType == "AssemblyInstruction") {
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auto* i = static_cast<AssemblyInstruction*>(n);
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out << " " << toLower(i->opcode);
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if (!i->operands.empty()) {
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out << " ";
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for (size_t k = 0; k < i->operands.size(); ++k) {
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out << i->operands[k];
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if (k + 1 < i->operands.size()) out << ", ";
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}
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}
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out << "\n";
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} else if (n->conceptType == "AssemblyDirective") {
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auto* d = static_cast<AssemblyDirective*>(n);
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out << " " << emitDirective(*d) << "\n";
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}
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}
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}
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static void emitModuleDirectives(const Module& module, std::ostringstream& out) {
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for (auto* s : module.getChildren("statements")) {
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if (s->conceptType == "AssemblyDirective") {
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auto* d = static_cast<AssemblyDirective*>(s);
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out << emitDirective(*d) << "\n";
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} else if (s->conceptType == "NamespaceDeclaration") {
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auto* ns = static_cast<NamespaceDeclaration*>(s);
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if (!ns->name.empty()) out << ns->name << "\n";
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for (auto* b : ns->getChildren("body")) {
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if (b->conceptType == "AssemblyDirective") {
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auto* d = static_cast<AssemblyDirective*>(b);
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out << emitDirective(*d) << "\n";
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}
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}
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}
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}
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}
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};
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147
editor/tests/step463_test.cpp
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147
editor/tests/step463_test.cpp
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@@ -0,0 +1,147 @@
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// Step 463: Assembly Generator Tests (12 tests)
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#include "ast/ArmAssemblyParser.h"
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#include "ast/AssemblyGenerator.h"
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#include "ast/X86AssemblyParser.h"
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#include <iostream>
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static int passed = 0, failed = 0;
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#define TEST(name) { std::cout << " " << #name << "... "; }
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#define PASS() { std::cout << "PASS\n"; ++passed; }
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#define FAIL(msg) { std::cout << "FAIL: " << msg << "\n"; ++failed; }
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#define CHECK(cond, msg) if (!(cond)) { FAIL(msg); return; } else {}
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void test_generate_x86_intel_contains_expected_instructions() {
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TEST(generate_x86_intel_contains_expected_instructions);
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auto mod = X86AssemblyParser::parseX86(".text\nmain:\n mov rax, rbx\n ret\n");
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auto out = AssemblyGenerator::generateX86(*mod, X86OutputSyntax::Intel);
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CHECK(out.find("main:") != std::string::npos, "missing label");
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CHECK(out.find("mov rax, rbx") != std::string::npos, "missing intel mov");
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PASS();
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}
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void test_generate_x86_att_adds_register_sigils() {
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TEST(generate_x86_att_adds_register_sigils);
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auto mod = X86AssemblyParser::parseX86(".text\nmain:\n mov rax, rbx\n ret\n");
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auto out = AssemblyGenerator::generateX86(*mod, X86OutputSyntax::ATT);
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CHECK(out.find("mov %rax, %rbx") != std::string::npos, "missing AT&T register sigils");
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PASS();
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}
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void test_generate_x86_preserves_directives() {
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TEST(generate_x86_preserves_directives);
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auto mod = X86AssemblyParser::parseX86(".global main\n.text\nmain:\n ret\n");
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auto out = AssemblyGenerator::generateX86(*mod);
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CHECK(out.find(".global main") != std::string::npos, "missing .global");
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CHECK(out.find(".text") != std::string::npos, "missing .text");
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PASS();
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}
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void test_generate_arm_contains_lowercase_opcodes() {
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TEST(generate_arm_contains_lowercase_opcodes);
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auto mod = ArmAssemblyParser::parseArm(".text\nmain:\n MOV r0, r1\n RET\n");
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auto out = AssemblyGenerator::generateArm(*mod);
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CHECK(out.find("mov r0, r1") != std::string::npos, "missing arm mov");
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CHECK(out.find("ret") != std::string::npos, "missing arm ret");
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PASS();
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}
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void test_generate_arm_preserves_sections() {
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TEST(generate_arm_preserves_sections);
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auto mod = ArmAssemblyParser::parseArm(".text\nmain:\n RET\n.data\nv: .word 1\n");
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auto out = AssemblyGenerator::generateArm(*mod);
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CHECK(out.find(".text") != std::string::npos, "missing .text");
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CHECK(out.find(".data") != std::string::npos, "missing .data");
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PASS();
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}
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void test_translate_x86_to_arm_maps_mov_add_sub_cmp() {
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TEST(translate_x86_to_arm_maps_mov_add_sub_cmp);
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std::vector<AssemblyInstruction> x86 = {
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AssemblyInstruction("mov", {"rax", "rbx"}),
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AssemblyInstruction("add", {"rax", "1"}),
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AssemblyInstruction("sub", {"rax", "2"}),
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AssemblyInstruction("cmp", {"rax", "rbx"})
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};
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auto arm = AssemblyGenerator::translateX86ToArmSimple(x86);
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CHECK(arm.size() == 4, "wrong mapped size");
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CHECK(arm[0].opcode == "mov", "mov mapping failed");
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CHECK(arm[1].opcode == "add", "add mapping failed");
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CHECK(arm[2].opcode == "sub", "sub mapping failed");
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CHECK(arm[3].opcode == "cmp", "cmp mapping failed");
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PASS();
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}
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void test_translate_x86_to_arm_maps_jmp_and_call() {
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TEST(translate_x86_to_arm_maps_jmp_and_call);
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std::vector<AssemblyInstruction> x86 = {
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AssemblyInstruction("jmp", {"label"}),
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AssemblyInstruction("call", {"helper"})
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};
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auto arm = AssemblyGenerator::translateX86ToArmSimple(x86);
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CHECK(arm[0].opcode == "b", "jmp should map to b");
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CHECK(arm[1].opcode == "bl", "call should map to bl");
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PASS();
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}
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void test_translate_x86_to_arm_maps_ret() {
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TEST(translate_x86_to_arm_maps_ret);
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std::vector<AssemblyInstruction> x86 = { AssemblyInstruction("ret", {}) };
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auto arm = AssemblyGenerator::translateX86ToArmSimple(x86);
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CHECK(arm[0].opcode == "ret", "ret mapping failed");
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PASS();
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}
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void test_translate_unknown_opcode_passthrough() {
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TEST(translate_unknown_opcode_passthrough);
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std::vector<AssemblyInstruction> x86 = { AssemblyInstruction("nop", {}) };
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auto arm = AssemblyGenerator::translateX86ToArmSimple(x86);
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CHECK(arm[0].opcode == "nop", "unknown opcode should pass through");
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PASS();
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}
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void test_comment_prefix_x86() {
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TEST(comment_prefix_x86);
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CHECK(AssemblyGenerator::commentPrefix("x86") == "; ", "wrong x86 comment prefix");
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PASS();
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}
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void test_comment_prefix_arm() {
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TEST(comment_prefix_arm);
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CHECK(AssemblyGenerator::commentPrefix("arm") == "@ ", "wrong arm comment prefix");
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PASS();
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}
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void test_roundtrip_parse_generate_parse_x86() {
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TEST(roundtrip_parse_generate_parse_x86);
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std::string src = ".text\nmain:\n mov rax, rbx\n add rax, 1\n ret\n";
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auto mod1 = X86AssemblyParser::parseX86(src);
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auto gen = AssemblyGenerator::generateX86(*mod1);
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auto mod2 = X86AssemblyParser::parseX86(gen);
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CHECK(mod2->getChildren("functions").size() == 1, "roundtrip function count mismatch");
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auto* fn = static_cast<Function*>(mod2->getChildren("functions")[0]);
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CHECK(fn->getChildren("body").size() >= 4, "roundtrip body too small");
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PASS();
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}
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int main() {
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std::cout << "Step 463: Assembly Generator Tests\n";
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test_generate_x86_intel_contains_expected_instructions(); // 1
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test_generate_x86_att_adds_register_sigils(); // 2
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test_generate_x86_preserves_directives(); // 3
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test_generate_arm_contains_lowercase_opcodes(); // 4
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test_generate_arm_preserves_sections(); // 5
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test_translate_x86_to_arm_maps_mov_add_sub_cmp(); // 6
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test_translate_x86_to_arm_maps_jmp_and_call(); // 7
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test_translate_x86_to_arm_maps_ret(); // 8
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test_translate_unknown_opcode_passthrough(); // 9
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test_comment_prefix_x86(); // 10
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test_comment_prefix_arm(); // 11
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test_roundtrip_parse_generate_parse_x86(); // 12
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std::cout << "\nResults: " << passed << "/" << (passed + failed)
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<< " passed\n";
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return failed == 0 ? 0 : 1;
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}
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32
progress.md
32
progress.md
@@ -6138,3 +6138,35 @@ addressing modes, directives, and label/function shaping.
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**Architecture gate check:**
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- `editor/src/ast/ArmAssemblyParser.h` within header-size limit (`245` <= `600`)
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- `editor/tests/step462_test.cpp` within test-file size guidance (`173` lines)
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### Step 463: Assembly Generator — x86 + ARM
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**Status:** PASS (12/12 tests)
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Adds assembly code generation for x86 and ARM from AST, plus a simple
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cross-architecture instruction mapper for straightforward x86→ARM projection.
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**Files added:**
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- `editor/src/ast/AssemblyGenerator.h` — generator and mapper:
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- `generateX86` with Intel/AT&T syntax mode support
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- `generateArm` output path
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- `translateX86ToArmSimple` mapping for core opcodes (`mov/add/sub/cmp/jmp/call/ret`)
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- architecture comment prefixes (`x86 -> "; "`, `arm -> "@ "`)
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- directive/section emission from module and namespace-like section nodes
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- `editor/tests/step463_test.cpp` — 12 tests covering:
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- x86 Intel/AT&T generation behavior
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- ARM generation behavior
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- directive/section emission
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- x86→ARM opcode mapping including control flow
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- unknown-opcode passthrough
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- comment prefix semantics
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- parse→generate→parse roundtrip sanity check for x86
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- `editor/CMakeLists.txt` — `step463_test` target
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**Verification run:**
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- `cmake --build editor/build-native --target step463_test` — PASS
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- `./editor/build-native/step463_test` — PASS (12/12)
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- `./editor/build-native/step462_test` — PASS (12/12) regression coverage
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**Architecture gate check:**
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- `editor/src/ast/AssemblyGenerator.h` within header-size limit (`167` <= `600`)
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- `editor/tests/step463_test.cpp` within test-file size guidance (`147` lines)
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