Complete step462 ARM assembly parser with tests
This commit is contained in:
Bill
@@ -3037,4 +3037,13 @@ target_link_libraries(step461_test PRIVATE
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tree_sitter_javascript tree_sitter_typescript
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tree_sitter_java tree_sitter_rust tree_sitter_go)
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add_executable(step462_test tests/step462_test.cpp)
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target_include_directories(step462_test PRIVATE src)
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target_link_libraries(step462_test PRIVATE
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nlohmann_json::nlohmann_json
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unofficial::tree-sitter::tree-sitter
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tree_sitter_python tree_sitter_cpp tree_sitter_elisp
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tree_sitter_javascript tree_sitter_typescript
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tree_sitter_java tree_sitter_rust tree_sitter_go)
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# Step 12: Dear ImGui shell scaffolding created (main.cpp exists but not built due to dependencies)
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245
editor/src/ast/ArmAssemblyParser.h
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245
editor/src/ast/ArmAssemblyParser.h
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@@ -0,0 +1,245 @@
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#pragma once
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// Step 462: ARM Assembly Parser
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// Supports ARM/AArch64 core instruction/directive/label forms.
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#include "AssemblyNodes.h"
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#include "EnumNamespaceNodes.h"
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#include "Function.h"
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#include "Module.h"
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#include "Parser.h"
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#include <algorithm>
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#include <cctype>
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#include <regex>
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#include <set>
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#include <sstream>
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#include <string>
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class ArmAssemblyParser {
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public:
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static std::unique_ptr<Module> parseArm(const std::string& source) {
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auto result = parseArmWithDiagnostics(source);
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return std::move(result.module);
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}
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static ParseResult parseArmWithDiagnostics(const std::string& source) {
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ParseResult out;
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auto module = std::make_unique<Module>();
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module->id = IdGenerator::next("mod");
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module->name = "parsed_arm_module";
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module->targetLanguage = "arm_asm";
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std::set<std::string> globalLabels;
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NamespaceDeclaration* currentSection = nullptr;
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Function* currentFunction = nullptr;
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std::istringstream in(source);
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std::string raw;
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int lineNo = 0;
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while (std::getline(in, raw)) {
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++lineNo;
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std::string line = trim(stripComment(raw));
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if (line.empty()) continue;
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if (isDirective(line)) {
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auto dir = parseDirective(line);
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if (dir.type == AssemblyDirectiveType::Global) {
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std::string g = trim(dir.value);
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if (!g.empty()) globalLabels.insert(stripSigils(g));
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}
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if (dir.type == AssemblyDirectiveType::Text ||
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dir.type == AssemblyDirectiveType::Data ||
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dir.type == AssemblyDirectiveType::Section) {
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std::string sectionName = dir.type == AssemblyDirectiveType::Section
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? trim(dir.value) : directiveTypeToString(dir.type);
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currentSection = new NamespaceDeclaration(IdGenerator::next("ns"), sectionName);
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module->addChild("statements", currentSection);
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currentFunction = nullptr;
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}
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auto* d = new AssemblyDirective(dir.type, dir.value);
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if (currentSection) currentSection->addChild("body", d);
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else module->addChild("statements", d);
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continue;
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}
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if (isLabel(line)) {
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std::string name = parseLabelName(line);
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bool isGlobal = globalLabels.count(name) > 0;
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auto* label = new AssemblyLabel(name, isGlobal);
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currentFunction = new Function(IdGenerator::next("fn"), name);
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currentFunction->addChild("body", label);
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module->addChild("functions", currentFunction);
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continue;
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}
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auto inst = parseInstruction(line);
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if (inst.opcode.empty()) {
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out.diagnostics.push_back({lineNo, 1, "Unrecognized assembly line: " + line, "warning"});
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continue;
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}
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if (!isKnownOpcode(inst.opcode)) {
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out.diagnostics.push_back({lineNo, 1, "Unknown opcode: " + inst.opcode, "warning"});
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}
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auto* node = new AssemblyInstruction(inst.opcode, inst.operands);
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node->registers = std::move(inst.registers);
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node->memoryOperands = std::move(inst.memoryOperands);
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if (!currentFunction) {
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currentFunction = new Function(IdGenerator::next("fn"), "_entry");
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module->addChild("functions", currentFunction);
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}
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currentFunction->addChild("body", node);
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}
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out.module = std::move(module);
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return out;
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}
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private:
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static std::string trim(const std::string& s) {
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size_t start = s.find_first_not_of(" \t\r\n");
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if (start == std::string::npos) return "";
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size_t end = s.find_last_not_of(" \t\r\n");
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return s.substr(start, end - start + 1);
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}
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static std::string stripComment(const std::string& line) {
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size_t at = line.find('@');
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size_t sem = line.find(';');
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size_t slash = line.find("//");
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size_t cut = std::string::npos;
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if (at != std::string::npos) cut = at;
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if (sem != std::string::npos) cut = cut == std::string::npos ? sem : std::min(cut, sem);
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if (slash != std::string::npos) cut = cut == std::string::npos ? slash : std::min(cut, slash);
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return cut == std::string::npos ? line : line.substr(0, cut);
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}
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static bool isDirective(const std::string& line) {
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return !line.empty() && line[0] == '.';
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}
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static bool isLabel(const std::string& line) {
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return !line.empty() && line.back() == ':';
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}
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static std::string stripSigils(const std::string& token) {
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std::string out = token;
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while (!out.empty() && (out[0] == '#' || out[0] == '%')) out.erase(out.begin());
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return out;
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}
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static std::string parseLabelName(const std::string& line) {
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std::string n = line.substr(0, line.size() - 1);
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return stripSigils(trim(n));
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}
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static AssemblyDirective parseDirective(const std::string& line) {
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size_t sp = line.find_first_of(" \t");
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std::string head = sp == std::string::npos ? line : line.substr(0, sp);
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std::string tail = sp == std::string::npos ? "" : trim(line.substr(sp + 1));
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return AssemblyDirective(directiveTypeFromString(head), tail);
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}
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static std::vector<std::string> splitOperands(const std::string& s) {
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std::vector<std::string> out;
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std::string cur;
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int bracketDepth = 0;
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for (char c : s) {
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if (c == '[') ++bracketDepth;
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if (c == ']') --bracketDepth;
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if (c == ',' && bracketDepth == 0) {
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out.push_back(trim(cur));
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cur.clear();
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} else {
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cur.push_back(c);
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}
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}
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if (!trim(cur).empty()) out.push_back(trim(cur));
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return out;
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}
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static bool isRegisterName(const std::string& raw) {
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std::string r = toLower(stripSigils(raw));
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if (r == "sp" || r == "lr" || r == "pc") return true;
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if (r.size() >= 2 && (r[0] == 'r' || r[0] == 'x')) {
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for (size_t i = 1; i < r.size(); ++i) {
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if (!std::isdigit(static_cast<unsigned char>(r[i]))) return false;
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}
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int v = std::stoi(r.substr(1));
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if (r[0] == 'r') return v >= 0 && v <= 15;
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return v >= 0 && v <= 30;
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}
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return false;
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}
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static int registerSizeBits(const std::string& raw) {
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std::string r = toLower(stripSigils(raw));
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if (r == "sp" || r == "lr" || r == "pc") return 64;
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if (!r.empty() && r[0] == 'x') return 64;
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return 32;
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}
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static int parseInt(const std::string& raw) {
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std::string t = trim(stripSigils(raw));
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if (t.empty()) return 0;
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try {
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size_t idx = 0;
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int base = 10;
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if (t.size() > 2 && t[0] == '0' && (t[1] == 'x' || t[1] == 'X')) base = 16;
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return std::stoi(t, &idx, base);
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} catch (...) {
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return 0;
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}
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}
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static bool parseMemoryOperand(const std::string& op, AssemblyMemoryOperand& out) {
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if (op.size() < 2 || op.front() != '[' || op.back() != ']') return false;
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std::string inner = trim(op.substr(1, op.size() - 2)); // r0, #4 OR r0, r1, LSL #2
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std::vector<std::string> parts = splitOperands(inner);
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if (parts.empty()) return false;
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out.baseRegister = stripSigils(trim(parts[0]));
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if (parts.size() >= 2) {
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std::string p1 = trim(parts[1]);
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if (isRegisterName(p1)) out.indexRegister = stripSigils(p1);
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else out.offset = parseInt(p1);
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}
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if (parts.size() >= 3) {
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std::string p2 = toLower(trim(parts[2]));
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std::regex lslRx(R"(lsl\s*#?(\d+))");
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std::smatch m;
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if (std::regex_search(p2, m, lslRx)) out.scale = parseInt(m[1].str());
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}
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return true;
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}
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static AssemblyInstruction parseInstruction(const std::string& line) {
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size_t sp = line.find_first_of(" \t");
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std::string op = toLower(trim(sp == std::string::npos ? line : line.substr(0, sp)));
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std::string ops = sp == std::string::npos ? "" : trim(line.substr(sp + 1));
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AssemblyInstruction inst(op, splitOperands(ops));
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for (const auto& operand : inst.operands) {
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if (isRegisterName(operand)) {
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inst.registers.emplace_back(stripSigils(operand), registerSizeBits(operand));
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continue;
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}
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AssemblyMemoryOperand mem;
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if (parseMemoryOperand(operand, mem)) inst.memoryOperands.push_back(mem);
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}
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return inst;
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}
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static std::string toLower(std::string s) {
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std::transform(s.begin(), s.end(), s.begin(),
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[](unsigned char c){ return static_cast<char>(std::tolower(c)); });
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return s;
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}
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static bool isKnownOpcode(const std::string& op) {
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static const std::set<std::string> known = {
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"mov", "add", "sub", "ldr", "str", "b", "bl", "cmp",
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"beq", "bne", "bgt", "blt", "bge", "ble", "ret"
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};
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return known.count(op) > 0;
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}
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};
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173
editor/tests/step462_test.cpp
Normal file
173
editor/tests/step462_test.cpp
Normal file
@@ -0,0 +1,173 @@
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// Step 462: ARM Assembly Parser Tests (12 tests)
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#include "ast/ArmAssemblyParser.h"
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#include "ast/AssemblyNodes.h"
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#include "ast/EnumNamespaceNodes.h"
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#include <iostream>
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static int passed = 0, failed = 0;
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#define TEST(name) { std::cout << " " << #name << "... "; }
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#define PASS() { std::cout << "PASS\n"; ++passed; }
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#define FAIL(msg) { std::cout << "FAIL: " << msg << "\n"; ++failed; }
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#define CHECK(cond, msg) if (!(cond)) { FAIL(msg); return; } else {}
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void test_parse_arm_basic_instructions() {
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TEST(parse_arm_basic_instructions);
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std::string src = ".text\nmain:\n MOV r0, r1\n ADD r0, r0, #1\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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CHECK(mod->getChildren("functions").size() == 1, "expected one function");
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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CHECK(fn->name == "main", "expected main function");
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CHECK(fn->getChildren("body").size() >= 3, "expected label + instructions");
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PASS();
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}
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void test_parse_aarch64_registers() {
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TEST(parse_aarch64_registers);
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std::string src = ".text\nmain:\n MOV x0, x1\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->registers.size() >= 2, "expected register extraction");
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CHECK(i->registers[0].sizeBits == 64, "expected 64-bit x register");
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PASS();
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}
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void test_parse_arm32_registers() {
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TEST(parse_arm32_registers);
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std::string src = ".text\nmain:\n MOV r0, r1\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->registers.size() >= 2, "expected register extraction");
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CHECK(i->registers[0].sizeBits == 32, "expected 32-bit r register");
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PASS();
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}
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void test_parse_special_registers_sp_lr_pc() {
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TEST(parse_special_registers_sp_lr_pc);
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std::string src = ".text\nmain:\n MOV sp, lr\n MOV x0, pc\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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int special = 0;
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for (auto* n : fn->getChildren("body")) {
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if (n->conceptType != "AssemblyInstruction") continue;
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auto* i = static_cast<AssemblyInstruction*>(n);
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for (const auto& r : i->registers) {
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if (r.name == "sp" || r.name == "lr" || r.name == "pc") ++special;
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}
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}
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CHECK(special >= 2, "expected special register recognition");
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PASS();
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}
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void test_parse_memory_mode_base_only() {
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TEST(parse_memory_mode_base_only);
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std::string src = ".text\nmain:\n LDR r0, [r1]\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->memoryOperands.size() == 1, "expected memory operand");
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CHECK(i->memoryOperands[0].baseRegister == "r1", "expected base r1");
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PASS();
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}
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void test_parse_memory_mode_base_plus_offset() {
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TEST(parse_memory_mode_base_plus_offset);
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std::string src = ".text\nmain:\n LDR r0, [r1, #4]\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->memoryOperands.size() == 1, "expected memory operand");
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CHECK(i->memoryOperands[0].offset == 4, "expected offset 4");
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PASS();
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}
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void test_parse_memory_mode_index_shifted() {
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TEST(parse_memory_mode_index_shifted);
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std::string src = ".text\nmain:\n STR x0, [x1, x2, LSL #2]\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->memoryOperands.size() == 1, "expected memory operand");
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CHECK(i->memoryOperands[0].indexRegister == "x2", "expected index x2");
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CHECK(i->memoryOperands[0].scale == 2, "expected scale 2");
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PASS();
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}
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void test_parse_directives_global_text_data_word_align() {
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TEST(parse_directives_global_text_data_word_align);
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std::string src = ".global main\n.text\nmain:\n RET\n.data\nval: .word 1\n.align 4\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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int directives = 0;
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for (auto* s : mod->getChildren("statements")) {
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if (s->conceptType == "AssemblyDirective") ++directives;
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if (s->conceptType == "NamespaceDeclaration") {
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auto* ns = static_cast<NamespaceDeclaration*>(s);
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directives += static_cast<int>(ns->getChildren("body").size());
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}
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}
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CHECK(directives >= 4, "expected directive parsing");
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PASS();
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}
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void test_parse_branch_and_call_opcodes() {
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TEST(parse_branch_and_call_opcodes);
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std::string src = ".text\nmain:\n B loop\n BL helper\n CMP r0, r1\nloop:\n RET\nhelper:\n RET\n";
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auto res = ArmAssemblyParser::parseArmWithDiagnostics(src);
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CHECK(res.diagnostics.empty(), "expected known opcodes only");
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PASS();
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}
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void test_labels_and_global_flags() {
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TEST(labels_and_global_flags);
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std::string src = ".global main\n.text\nmain:\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* lbl = static_cast<AssemblyLabel*>(fn->getChildren("body")[0]);
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CHECK(lbl->isGlobal, "expected global label");
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PASS();
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}
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void test_section_namespaces_created() {
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TEST(section_namespaces_created);
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std::string src = ".text\nmain:\n RET\n.data\nx: .word 1\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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int nsCount = 0;
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for (auto* s : mod->getChildren("statements")) {
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if (s->conceptType == "NamespaceDeclaration") ++nsCount;
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}
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CHECK(nsCount >= 2, "expected .text and .data namespaces");
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PASS();
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}
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void test_unknown_opcode_warning_emitted() {
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TEST(unknown_opcode_warning_emitted);
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std::string src = ".text\nmain:\n FROB r0, r1\n RET\n";
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auto res = ArmAssemblyParser::parseArmWithDiagnostics(src);
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CHECK(!res.diagnostics.empty(), "expected warning diagnostics");
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CHECK(res.diagnostics[0].severity == "warning", "expected warning severity");
|
||||
PASS();
|
||||
}
|
||||
|
||||
int main() {
|
||||
std::cout << "Step 462: ARM Assembly Parser Tests\n";
|
||||
|
||||
test_parse_arm_basic_instructions(); // 1
|
||||
test_parse_aarch64_registers(); // 2
|
||||
test_parse_arm32_registers(); // 3
|
||||
test_parse_special_registers_sp_lr_pc(); // 4
|
||||
test_parse_memory_mode_base_only(); // 5
|
||||
test_parse_memory_mode_base_plus_offset(); // 6
|
||||
test_parse_memory_mode_index_shifted(); // 7
|
||||
test_parse_directives_global_text_data_word_align(); // 8
|
||||
test_parse_branch_and_call_opcodes(); // 9
|
||||
test_labels_and_global_flags(); // 10
|
||||
test_section_namespaces_created(); // 11
|
||||
test_unknown_opcode_warning_emitted(); // 12
|
||||
|
||||
std::cout << "\nResults: " << passed << "/" << (passed + failed)
|
||||
<< " passed\n";
|
||||
return failed == 0 ? 0 : 1;
|
||||
}
|
||||
36
progress.md
36
progress.md
@@ -6102,3 +6102,39 @@ addressing extraction.
|
||||
**Architecture gate check:**
|
||||
- `editor/src/ast/X86AssemblyParser.h` within header-size limit (`299` <= `600`)
|
||||
- `editor/tests/step461_test.cpp` within test-file size guidance (`186` lines)
|
||||
|
||||
### Step 462: ARM Assembly Parser
|
||||
**Status:** PASS (12/12 tests)
|
||||
|
||||
Implements ARM/AArch64 assembly parsing for core instructions, registers,
|
||||
addressing modes, directives, and label/function shaping.
|
||||
|
||||
**Files added:**
|
||||
- `editor/src/ast/ArmAssemblyParser.h` — ARM parser:
|
||||
- parses ARM/AArch64 instructions (`mov`, `add`, `sub`, `ldr`, `str`, `b`,
|
||||
`bl`, `cmp`, conditional branches, `ret`)
|
||||
- register recognition for `r0-r15`, `x0-x30`, `sp`, `lr`, `pc`
|
||||
- ARM memory addressing extraction:
|
||||
- `[r0]`
|
||||
- `[r0, #4]`
|
||||
- `[r0, r1, LSL #2]`
|
||||
- directive handling (`.global`, `.text`, `.data`, `.word`, `.align`, `.section`)
|
||||
- section-as-namespace shaping via `NamespaceDeclaration`
|
||||
- warning diagnostics for unknown opcodes
|
||||
- `editor/tests/step462_test.cpp` — 12 tests covering:
|
||||
- ARM and AArch64 instruction/register parsing
|
||||
- special register handling
|
||||
- all required addressing forms
|
||||
- directive and section handling
|
||||
- branch/call opcode coverage
|
||||
- unknown-opcode warning behavior
|
||||
- `editor/CMakeLists.txt` — `step462_test` target
|
||||
|
||||
**Verification run:**
|
||||
- `cmake --build editor/build-native --target step462_test` — PASS
|
||||
- `./editor/build-native/step462_test` — PASS (12/12)
|
||||
- `./editor/build-native/step461_test` — PASS (12/12) regression coverage
|
||||
|
||||
**Architecture gate check:**
|
||||
- `editor/src/ast/ArmAssemblyParser.h` within header-size limit (`245` <= `600`)
|
||||
- `editor/tests/step462_test.cpp` within test-file size guidance (`173` lines)
|
||||
|
||||
Reference in New Issue
Block a user