174 lines
7.2 KiB
C++
174 lines
7.2 KiB
C++
// Step 462: ARM Assembly Parser Tests (12 tests)
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#include "ast/ArmAssemblyParser.h"
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#include "ast/AssemblyNodes.h"
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#include "ast/EnumNamespaceNodes.h"
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#include <iostream>
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static int passed = 0, failed = 0;
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#define TEST(name) { std::cout << " " << #name << "... "; }
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#define PASS() { std::cout << "PASS\n"; ++passed; }
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#define FAIL(msg) { std::cout << "FAIL: " << msg << "\n"; ++failed; }
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#define CHECK(cond, msg) if (!(cond)) { FAIL(msg); return; } else {}
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void test_parse_arm_basic_instructions() {
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TEST(parse_arm_basic_instructions);
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std::string src = ".text\nmain:\n MOV r0, r1\n ADD r0, r0, #1\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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CHECK(mod->getChildren("functions").size() == 1, "expected one function");
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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CHECK(fn->name == "main", "expected main function");
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CHECK(fn->getChildren("body").size() >= 3, "expected label + instructions");
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PASS();
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}
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void test_parse_aarch64_registers() {
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TEST(parse_aarch64_registers);
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std::string src = ".text\nmain:\n MOV x0, x1\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->registers.size() >= 2, "expected register extraction");
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CHECK(i->registers[0].sizeBits == 64, "expected 64-bit x register");
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PASS();
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}
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void test_parse_arm32_registers() {
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TEST(parse_arm32_registers);
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std::string src = ".text\nmain:\n MOV r0, r1\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->registers.size() >= 2, "expected register extraction");
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CHECK(i->registers[0].sizeBits == 32, "expected 32-bit r register");
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PASS();
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}
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void test_parse_special_registers_sp_lr_pc() {
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TEST(parse_special_registers_sp_lr_pc);
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std::string src = ".text\nmain:\n MOV sp, lr\n MOV x0, pc\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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int special = 0;
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for (auto* n : fn->getChildren("body")) {
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if (n->conceptType != "AssemblyInstruction") continue;
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auto* i = static_cast<AssemblyInstruction*>(n);
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for (const auto& r : i->registers) {
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if (r.name == "sp" || r.name == "lr" || r.name == "pc") ++special;
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}
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}
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CHECK(special >= 2, "expected special register recognition");
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PASS();
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}
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void test_parse_memory_mode_base_only() {
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TEST(parse_memory_mode_base_only);
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std::string src = ".text\nmain:\n LDR r0, [r1]\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->memoryOperands.size() == 1, "expected memory operand");
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CHECK(i->memoryOperands[0].baseRegister == "r1", "expected base r1");
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PASS();
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}
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void test_parse_memory_mode_base_plus_offset() {
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TEST(parse_memory_mode_base_plus_offset);
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std::string src = ".text\nmain:\n LDR r0, [r1, #4]\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->memoryOperands.size() == 1, "expected memory operand");
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CHECK(i->memoryOperands[0].offset == 4, "expected offset 4");
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PASS();
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}
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void test_parse_memory_mode_index_shifted() {
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TEST(parse_memory_mode_index_shifted);
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std::string src = ".text\nmain:\n STR x0, [x1, x2, LSL #2]\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* i = static_cast<AssemblyInstruction*>(fn->getChildren("body")[1]);
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CHECK(i->memoryOperands.size() == 1, "expected memory operand");
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CHECK(i->memoryOperands[0].indexRegister == "x2", "expected index x2");
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CHECK(i->memoryOperands[0].scale == 2, "expected scale 2");
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PASS();
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}
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void test_parse_directives_global_text_data_word_align() {
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TEST(parse_directives_global_text_data_word_align);
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std::string src = ".global main\n.text\nmain:\n RET\n.data\nval: .word 1\n.align 4\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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int directives = 0;
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for (auto* s : mod->getChildren("statements")) {
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if (s->conceptType == "AssemblyDirective") ++directives;
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if (s->conceptType == "NamespaceDeclaration") {
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auto* ns = static_cast<NamespaceDeclaration*>(s);
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directives += static_cast<int>(ns->getChildren("body").size());
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}
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}
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CHECK(directives >= 4, "expected directive parsing");
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PASS();
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}
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void test_parse_branch_and_call_opcodes() {
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TEST(parse_branch_and_call_opcodes);
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std::string src = ".text\nmain:\n B loop\n BL helper\n CMP r0, r1\nloop:\n RET\nhelper:\n RET\n";
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auto res = ArmAssemblyParser::parseArmWithDiagnostics(src);
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CHECK(res.diagnostics.empty(), "expected known opcodes only");
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PASS();
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}
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void test_labels_and_global_flags() {
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TEST(labels_and_global_flags);
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std::string src = ".global main\n.text\nmain:\n RET\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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auto* fn = static_cast<Function*>(mod->getChildren("functions")[0]);
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auto* lbl = static_cast<AssemblyLabel*>(fn->getChildren("body")[0]);
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CHECK(lbl->isGlobal, "expected global label");
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PASS();
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}
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void test_section_namespaces_created() {
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TEST(section_namespaces_created);
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std::string src = ".text\nmain:\n RET\n.data\nx: .word 1\n";
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auto mod = ArmAssemblyParser::parseArm(src);
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int nsCount = 0;
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for (auto* s : mod->getChildren("statements")) {
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if (s->conceptType == "NamespaceDeclaration") ++nsCount;
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}
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CHECK(nsCount >= 2, "expected .text and .data namespaces");
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PASS();
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}
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void test_unknown_opcode_warning_emitted() {
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TEST(unknown_opcode_warning_emitted);
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std::string src = ".text\nmain:\n FROB r0, r1\n RET\n";
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auto res = ArmAssemblyParser::parseArmWithDiagnostics(src);
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CHECK(!res.diagnostics.empty(), "expected warning diagnostics");
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CHECK(res.diagnostics[0].severity == "warning", "expected warning severity");
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PASS();
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}
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int main() {
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std::cout << "Step 462: ARM Assembly Parser Tests\n";
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test_parse_arm_basic_instructions(); // 1
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test_parse_aarch64_registers(); // 2
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test_parse_arm32_registers(); // 3
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test_parse_special_registers_sp_lr_pc(); // 4
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test_parse_memory_mode_base_only(); // 5
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test_parse_memory_mode_base_plus_offset(); // 6
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test_parse_memory_mode_index_shifted(); // 7
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test_parse_directives_global_text_data_word_align(); // 8
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test_parse_branch_and_call_opcodes(); // 9
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test_labels_and_global_flags(); // 10
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test_section_namespaces_created(); // 11
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test_unknown_opcode_warning_emitted(); // 12
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std::cout << "\nResults: " << passed << "/" << (passed + failed)
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<< " passed\n";
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return failed == 0 ? 0 : 1;
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}
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